1. Field of the Invention
The present invention relates to a Static Random Access Memory (SRAM) and more particularly to an SRAM including a high-resistance element for loading.
2. Description of the Background Art
Conventionally, an SRAM is known as a volatile semiconductor memory device. An SRAM has memory cells at intersections of complementary data lines, or bit lines, and word lines arranged in a matrix. Each memory cell is composed of a flipflop circuit and two access transistors. By the flipflop circuit, two cross-coupled storage nodes are composed. An SRAM has a bistable state, (High, Low) or (Low, High), which state is kept as long as a predetermined power supply voltage (Vcc) is provided.
A semiconductor region of one access transistor is connected to a storage node, or an input/output terminal of the flipflop circuit, while a semiconductor region of the other access transistor is connected to a complementary data line. Each access transistor has a gate electrode connected to a word line, which controls conduction/non-conduction of the access transistor.
A flipflop circuit is composed of two driver transistors and two load elements. In a conventional SRAM, as disclosed in Japanese Patent Laying-Open No. 60-138956, for example, a high-resistance element has been used for loading which is made of high-resistance, polycrystalline silicon.
Recently, with an increasing demand for larger capacities, there has been a need to reduce the size of a memory cell. Accordingly, the above-mentioned high-resistance, polycrystalline silicon has been reduced in size, making it difficult to secure a sufficient length of high-resistance portion. Insufficient length of the high-resistance portion leads to an insufficient resistance value, which results in a large amount of current flowing through the high-resistance portion connected to a storage node at a Low level when the SRAM is on standby. Consequently, power consumption has been undesirably increased.
In view of such a problems there have been proposed measures for securing an adequate length of high-resistance portion in Japanese Patent Laying-Open Nos. 3-165560 and 61-283161.
Japanese Patent Laying-Open No. 3-165560 discloses a solution in which a resistance element is formed to extend onto an adjacent memory cell, whereby it becomes possible to secure a high-resistance portion with a sufficient length. However, since each resistance element is arranged in a horizontal direction here, an interval between interconnections is narrow, hindering further miniaturization.
Japanese Patent Laying-Open No. 61-283161 discloses a solution in which one high-resistance element is formed by connecting two, upper and lower, layers of high-resistance interconnections to each other. In this case, however, a failure in connection between the high-resistance interconnections may cause variation in high resistance values and, possibly, decrease in the yield.
In addition to the problems described above, there may be problems as follows. By reducing the size of a memory cell, the storage capacity of a storage node becomes inadequate. Reduction in the memory cell size leads to reduction of the size of each element connected to the storage node. Accordingly, parasitic capacitances of those elements also decrease. The storage capacity of a storage node includes parasitic capacitance of any element connected thereto. Therefore, as the parasitic capacitance of each element decreases, the storage capacity of the storage node of a memory cell becomes smaller than in a conventional case. Such a reduction in storage capacity may cause a soft error problem.
Here, a soft error means a random error occurring due to the inversion of information stored in a memory cell, which is caused by the event that electrons out of electron-hole pairs generated by incident .alpha. rays from the outside, e.g. from packaging materials, are attracted to a storage node in a memory cell.